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4801 Spicewood
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Suite #150,
Austin, TX 78759
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Tel: 512.372.8887
Fax: 512.372.8889
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 ADVANCED PACKAGING UPDATE:
Market and Technology Trends
Vol. 4, 2008
Volume 4 of the Advanced Packaging Update for 2008 features special coverage of the market with a forecast for units of BGAs and CSPs by package construction. The BGA market is divided into plastic, tape, and ceramic structures. The CSP market is divided into laminate, flex circuit, and leadframe substrates. Unit growth projections are provided for stacked die CSP and package-on-package (PoP) shipments. An economic analysis examines macroeconomic trends and their impact on the semiconductor packaging and assembly industry. A market growth analysis based on input from both captive and merchant assembly operations is provided. The impact of the downturn on unit volumes is explained. Key applications and drivers for the recovery are highlighted. A section on co-design is included.
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Advanced Packaging Update: Market and Technology Trends
Vol. 4, 2008 |
| File size: 56.0 kb |
Published: April 2009. |
| Table of Contents |
| 1 |
Industry and Economic Trends |
| 1.1 |
Economic Trends |
| 1.1.1 |
Macroeconomic Trends |
| 1.1.2 |
Signs of Recovery in the Electronics Industry |
| 1.1.3 |
China's Growth |
| 1.2 |
Semiconductor Packaging and Assembly |
| 2 |
BGA Applications and Market Growth |
| 2.1 |
Personal Computers |
| 2.2 |
Game Machines |
| 2.3 |
Workstation/Servers, Network Systems, and Telecommunications |
| 2.4 |
BGA Market Projections |
| 3 |
CSP Applications and Market Growth |
| 3.1 |
Mobile Phones |
| 3.2 |
Portable Games |
| 3.3 |
Leadframe CSPs |
| 3.4 |
Laminate and Flex Circuit CSPs |
| 3.5 |
Wafer Level Packages |
| 3.6 |
Stacked Die and Package-on-Package |
| 3.6.1 |
Technical Issues |
| 3.6.2 |
Future Trends |
| 3.6.2.1 |
Fan-in PoP |
| 3.6.2.2 |
Through Mold Via |
| 3.6.2.3 |
Solder-on-Pad |
| 3.6.2.4 |
Triple PoP |
| 3.6.2.5 |
Stackable Fan-out Wafer-Level Package |
| 3.6.2.6 |
Embedded Die PoP |
| 3.6.2.7 |
TSV-PoP |
| 3.6.3 |
Corporate Developments |
| 3.6.3.1 |
Advanced Semiconductor Engineering, Inc. (ASE) |
| 3.6.3.2 |
Amkor Technology, Inc. |
| 3.6.3.3 |
Infineon Technologies |
| 3.6.3.4 |
Kyushu Institute of Technology |
| 3.6.3.5 |
Nokia |
| 3.6.3.6 |
Panasonic Factory Solutions Co., Ltd. |
| 3.6.3.7 |
Renesas Technology |
| 3.6.3.8 |
Samsung Electronics Co., Ltd. |
| 3.6.3.9 |
Siliconware Precision Industries Co., Ltd. (SPIL) |
| 3.6.3.10 |
STATS ChipPAC, Ltd. |
| 3.6.3.11 |
Vertical Circuits, Inc. |
| 3.7 |
CSP Market Projections |
| 4 |
Co-Design and Co-Simulation of Chip, Package, and Board |
| 4.1 |
Co-Design |
| 4.2 |
Co-Simulation |
| 4.2.1 |
EDA Perspective |
| 4.2.2 |
User Perspective |
| 4.3 |
Corporate Activities |
| 4.3.1 |
Amkor |
| 4.3.2 |
Apache Design Solutions, Inc. |
| 4.3.3 |
Cadence Design Systems, Inc. |
| 4.3.4 |
Cisco Systems, Inc. |
| 4.3.5 |
LSI Corporation |
| 4.3.6 |
Mentor Graphics Corporation |
| 4.3.7 |
Nokia |
| 4.3.8 |
Sigrity, Inc. |
| 4.3.9 |
STATS ChipPAC, Ltd. |
| 4.3.10 |
Synopsys, Inc |
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2008 BGA and CSP Bibliography |
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References |
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| List of Figures |
| 1.1. |
Monthly U.S. housing starts. |
| 1.2. |
Semiconductor packaging and test subcontractor sales. |
| 1.3. |
Semiconductor packaging and test subcontractor CAPEX. |
| 2.1. |
Router board populated with BGAs. |
| 2.2. |
Flip chip as a percentage of 2008 PBGA shipments. |
| 2.3. |
Subcontractor growth in PBGA shipments. |
| 3.1. |
CSPs in Apple's iPhone 3G. |
| 3.2. |
Huawei's eMobile. |
| 3.3. |
Increasing die size and I/O count for WLPs. |
| 3.4. |
ASE's bottom PoP with embedded die. |
| 3.5. |
Warpage measurements on bottom PoP. |
| 3.6. |
Amkor's 24-die stack technical demonstration. |
| 3.7. |
Double-sided eWLB for stacking. |
| 3.8. |
Process flow for DFP-PW. |
| 3.9. |
Renesas SiP roadmap. |
| 3.10. |
Samsung's fan-in bottom PoP for dense memory stacks |
| 3.11. |
Solder joint cross-section of Samsung's fan-in PoP. |
| 3.12. |
SPIL's PoP structure. |
| 3.13. |
Cross-section of fan-in PoP. |
| 3.14. |
Cross-section of two-chip PiP. |
| 3.15. |
PoP market projections (millions of units). |
| 3.16. |
Subcontract assembly growth in CSPs. |
| 4.1. |
Sentinel platform for chip-package-board co-analysis. |
| 4.2. |
Silicon design costs as a driver for 3D IC. |
| 4.3. |
Global silicon interconnection and packaging. |
| 4.4. |
Evolution of the IC design flow to accommodate 3D IC |
| List of Tables |
| 2.1. |
Netbook PC Specifications |
| 2.2. |
PBGAs in Game Machines |
| 2.3 |
BGA Market Projections (millions of units) |
| 3.1 |
CSPs in PSP-3000 |
| 3.2. |
Die Stacks and Device Types in Production at Amkor |
| 3.3. |
Reliability Test Matrix for Samsung's Fan-in PoP |
| 3.4. |
Die Stacks and Device Types in Production at STATS ChipPAC |
| 3.5. |
Properties of STATS ChipPAC's Bottom fan-in PoP Test Vehicle |
| 3.6. |
Stack Heights and Device Types at VCI |
| 3.7. |
CSP Market Projections (millions of units) |
| 4.1. |
Selected Co-Design Tools |
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