Wafer level packaging (WLP) is often the most cost-effective approach for achieving miniaturization. However, using wafer level packaging for the wrong applications can be needlessly expensive. The significant differences between printed circuit board interconnect design rules and semiconductor interconnect design rules must be resolved by the package, and this presents unique challenges for wafer level packaging.
If miniaturization is not required, a wire bond package is usually the most cost-effective packaging approach. However, a modified wafer level packaging approach called fan-out wafer level packaging is one option that overcomes the traditional WLP I/O restriction. In many cases, fan-out wafer level packaging or flip chip packaging is the lowest cost solution for applications requiring a moderate number of I/Os with some package size constraints.
This paper compares the total packaging cost of the following four technologies:
- Fan-in wafer level packaging
- Fan-out wafer level packaging
The analysis is accomplished using a comprehensive activity based cost model for each of the four package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), fabrication activities (redistribution layer creation, inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) are modeled and verified using multiple industry sources.
- SavanSys develops the model software
- TechSearch helps with model calibration