2017 Flip Chip and WLP

Market Forecasts and Technology Analysis
order form
Driven by demand for thin, low-profile packages in smartphones, tablets, and wearable devices such as smart watches, fitness bands, and virtual reality headsets, fan-in WLPs are projected to have a >10% growth rate from 2015 to 2020.

FO-WLP shows a staggering growth rate of 82% over the same five-year period. FO-WLP growth is driven by the use in RF, audio CODEC, and power management ICs, and automotive radar, coupled with Apple’s adoption of TSMC’s InFO FO-WLP as the bottom package-on-package (PoP) in the iPhone 7. An update on FO-WLP panel processing and alternatives in the form of flip chip on coreless or thin core substrates is provided.

Driven by small size devices such as filters, low noise amplifiers, power amplifiers, and switches found in smartphones, flip chip growth shows >13% CAGR in unit volume. Flip chip applications, pitch trends, and assembly options are presented and the trends in Cu pillar are analyzed.

The report explores chip package interaction issues and discusses solutions. The 115-page report with full references provides forecasts for the flip chip wafer bumping market by application, device type, number of wafers, and die shipments. Merchant and captive capacity is included.

Forecasts for fan-in WLP, FO-WLP, and flip chip demand are projected in number of die and wafer shipments.

A set of PowerPoint slides accompanies the report.
  • Contents…
    • Executive Summary
    • 1 Technology Developments
      • 1.1 Fan-in and Fan-out WLPs
      • 1.2 FO-WLP Developments and Trends
        • 1.1.1 Chip Package Interaction Issues
        • 1.1.2 Singulation and Edge Protection
        • 1.1.3 Solder Ball Material and Pitch Trends
        • 1.2.1 Challenges with FO-WLP
        • 1.2.2 FO-WLP Versions
      • 1.3 Cost Reduction for FO-WLP
        • 1.3.1 Die Last Solutions
        • 1.3.2 Thin Core or Coreless Substrates
        • 1.3.3 Large Area Panels
        • Large Panel Process Considerations
          • 1.3.4.1 Economic Issues
          • 1.3.4.2 Technical Issues 
      • 1.4 Consortia for Panel Processing
        • 1.4 1 Fraunhofer’s FO-PLP Consortium
        • 1.4.2 FOPLP Large Panel Consortium
        • 1.4.3 Institute of Microelectronics
        • 1.4.4 Equipment/Material Developments
      • 1.5 Flip Chip Bump Trends
        • 1.5.1 Pb-free Bumps
        • 1.5.2 Cu Pillar
        • 1.5.3 Bump Pitch Trends
        • 1.5.4 CPI Issues
      • 1.6 Wafer Sizes
      • 1.7 Flip Chip Bump and WLP Price Trends
      • 1.8 Flip Chip Substrate Trends
        • 1.8.1 High Performance Applications
          • 1.8.1.1 Silicon Interposers
          • 1.8.1.2 Organic Interposers
          • 1.8.1.3 Glass Interposers
        • 1.8.2 Mobile Applications
          • 1.8.2.1 Coreless and Thin Core Substrates
          • 1.8.2.2 Leadframe and Molded Substrates 
      • 1.9 Underfill Material Trends
    • 2 Flip Chip Market Projections
      • 2.1 Wafer Bump Capacity
        • 2.1.1 Solder Bump Capacity
        • 2.1.2 Electroless NiAu
        • 2.1.3 Gold Bump Capacity
      • 2.2 Flip Chip Demand
        • 2.2.1 Solder Bumping Market Projections
        • 2.2.2 Cu Pillar Trends
        • 2.2.3 Gold Bumping Market Projections
        • 2.2.6 Flip Chip Application by Device Type
    • 3 WLP Trends and Market Projections
      • 3.1 Mobile Phones
      • 3.2 Tablets and Convertibles
      • 3.3 Wearables
      • 3.4 Fan-in WLP Market Forecast
      • 3.5 FO-WLP Drivers and Projections
        • 3.5.1 FO-WLP Market Forecast
      • 3.6 Fan-in WLP and FO-WLP Capacity
    • ​4 Wafer Bumping and WLP Service Providers
    • 5 Flip Chip Assembly and Equipment
      • 5.1 Flip Chip Bonders
    • 6 Contract Assembly Services
    • Appendix
      • Bumping and WLP Services
      • Underfill and ACF Materials
      • Assembly Service Suppliers
      • Placement & Bonding Equipment
      • Laminate Substrate Suppliers
  • Figures (partial list)…
    • Nepes FO-WLP process flow
    • Side view of InFO PoP and FC PoP
    • M-Series FO-WLP
    • ECP construction
    • PLP structure
    • Dedicated 300mm copper pillar capacity
    • Solder bump and copper pillar capacity
    • Copper pillar 300mm wafer demand
    • Flip chip for MR head in HDD
    • Cu pillar in TSMC’s InFO
    • Qualcomm MDM9645M with flip chip modem
    • Silicon photonics IC with flip chip
    • AMD’s Fiji with silicon interposer and HBM
    • Self-aligned photonic flip chip assembly
  • Tables (partial list)…
    • Typical Features for Flip Chip and WLP
    • Reconstituted Wafer FO-WLP Suppliers
    • FO-WLP Panel Sizes Under Development
    • Panel FO-WLP Cost Advantage
    • Fan-Out Wafer Level Package Panel Plan
    • IME’s Proposed Test Vehicles
    • Bump Pitch Trends
    • CPI Modulators in Flip Chip Assembly
    • Interposer Design Rule Comparison
    • UF Material Properties vs. Bump & Package Type
    • Underfill Process and Defects
    • Merchant and Captive Bump Capacity
    • Gold Bump Merchant & Captive Capacity Projections
    • Demand for Solder Bumped and Cu Pillar ICs
    • Flip Chip Die Size and Bump Examples
    • Demand for Gold Bumped ICs
    • Solder Bump Demand by Device Type
    • Flip Chip Examples in Mobile Products
    • RF FEMs in iPhone 7 (A1779)
    • WLPs in Apple iPhone 7
    • WLPs in Samsung Galaxy S7 Edge
    • WLPs in Huawei P9 Plus
    • WLPs in Xiaomi MiMax
    • WLPs in 12.9-inch iPad Pro Wi-Fi + Cellular
    • WLPs in iPad mini 4
    • WLPs in Fitness Trackers
    • WLPs in Apple Watch Series 2
    • Fan-in Wafer Level Package Demand
    • Fan-out WLP Examples
    • Companies Offering FO-WLP
    • Total FO-WLP Market Projections
    • High-Density FO-WLP Market Projections
    • Fan-in WLP Capacity and Demand Projections
    • FO-WLP Capacity and Demand Projections
    • Selected Merchant Wafer Bumping and WLP Offerings
    • Flip Chip Assembly Process and Defects
    • R&D and Low-Volume Flip Chip Bonders
    • Production Bonders for TCB
    • Bonders for FC Mass Reflow, FO-WLP, and Panel
    • Opto Bonders
    • Pick-and-Place Systems
    • Flip Chip Package Assembly Suppliers
Stacks Image 26050
brochure
  • Published January 2017
  • 115 pages
  • 17 figures / 38 tables
  • 85 PowerPoint slides
  • $4,995 single user
    $8,000 corporate license
Who We Are
TechSearch International is recognized around the world as a leading consulting company in the field of advanced semiconductor packaging and assembly, electronics manufacturing, and materials.
Network
Contact
  • email message
  • +1.512.372.8887
  • +1.512.372.8889
  • 4801 Spicewood Springs Rd, Ste 150
    Austin, TX 78759
    United States