Press Releases

TechSearch International Analysis Examines FO-WLP Developments and Sensor Packaging Trends

July 19, 2017

Mobile devices, specifically smartphones, represent the single greatest volume driver for MEMS and other sensors today. Sensors found in these products include electronic compasses, motion sensors, barometers, microphones, and fingerprint sensors. Package types include land grid arrays (LGAs,), leadframe packages such QFNs, and wafer level packages (WLPs.). Apple is expected to account for 28 percent of the total smartphone sensor market as a result of increased sensor adoption. With the trend toward smart factories, industrial applications are also expected to account for increased sensor demand.

New FO-WLP versions are targeting high-performance applications including networking, data centers, and artificial intelligence. Fan-out on substrate versions such as ASE’s Fan-Out Chip-on-Substrate (FOCoS), TSMC’s InFO_oS, and Amkor’s Silicon Wafer Integrated Fan-out Technology (SWIFT) are being considered as a low-cost heterogeneous integration alternative to silicon interposers. FO-WLP on substrate fills the interconnect gap between lower-density FO-WLP and the highest density silicon interposers.

The analysis is provided in the latest Advanced Packaging Update, an 84-page report with full references and an accompanying set of 46 PowerPoint slides. The report also provides results from TechSearch International’s annual survey on substrate design rules. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish.

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SEMI and TechSearch International Introduce Worldwide OSAT Manufacturing Sites Database

July 11, 2017

SEMI and TechSearch International have combined their expertise to offer an essential business resource for advanced semiconductor industry research; the Worldwide OSAT Manufacturing Sites Database enables users to track outsourced semiconductor assembly and testing (OSAT) suppliers’ packaging locations, offerings, and capabilities. The report tracks over 120 OSAT companies that provide packaging and testing services to the semiconductor industry.

The Worldwide OSAT Manufacturing Sites Database is a comprehensive report that offers access and insights into global OSAT facilities in China, Taiwan, Korea, Japan, Southeast Asia, Europe, and the Americas. The report highlights new and emerging packaging offerings by manufacturing location. Specific details tracked include:

•  Plant site location, technology, and capability (Packaging, Test, and other)
•  Packaging assembly service offered, such as BGA, specific leadframe type such as QFP, QFN, SO, flip chip bumping, WLP, Modules/SIP, and sensors

The Worldwide OSAT Manufacturing Sites Database is an extremely valuable business tool for anyone interested in device packaging. Packaging technology directly affects chip performance, reliability, and cost of semiconductors. Tracking advancements in packaging technology requires understanding companies’ offerings by location. The database includes:

•  120+ companies
•  280+ facilities
   -  over 90 facilities offering leadframe CSP
   -  over 20 bumping facilities, including 17 with 300mm wafer capacity
   -  over 45 facilities offering WLCSP technology
•  80 facilities in China, 78 in Taiwan, and 37 in Southeast Asia

The findings in the database are based on information gathered and compiled for over 120 companies globally. All of the information in the Worldwide OSAT Manufacturing Sites Database was collected by SEMI and TechSearch International. Report licenses are available for single-user and multi-users. SEMI members save 16 percent or more depending on the type of license. For more information about the Worldwide OSAT Manufacturing Sites Database or to ORDER a SAMPLE COPY, please click here. For pricing and ordering information, please click here.

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TechSearch International Analyzes High-Performance Package Trends

April 12, 2017

A variety of alternatives are challenging silicon’s role in advanced packaging interposers for high-performance applications. The first applications using silicon interposers with through silicon vias (TSVs) were field programmable gate arrays (FPGAs), followed by graphic processor units (GPUs). Though unit volumes have been small, the vast knowledge gained from these early pioneers is being applied to new generations of products. This year will see expansion into applications including networking systems and artificial intelligence applications. Future applications could include servers and datacenters, automotive electronics such as Advanced Driver Assistance Systems (ADAS), and virtual reality. However, shipments are lower than previously expected because lower cost alternatives are emerging.

The high cost of silicon interposers with TSVs has driven companies to develop alternatives that do not include the expensive process for TSVs. For example, Xilinx developed the Silicon-less Interconnect Technology (SLIT) solution. Amkor has introduced its version of the technology called Silicon Interposer-less Integrated Module (SLIM™). Intel’s Embedded Multi-die Interconnect Bridge (EMIB) uses a small silicon bridge embedded in an organic substrate, eliminating the need for a large silicon interposer with TSVs. Several companies are investigating the use of fan-out wafer level package (FO-WLP) for data centers and other high-performance applications.

The analysis is provided in the latest Advanced Packaging Update, a 42-page report with full references and an accompanying set of more than 40 PowerPoint slides. A forecast for silicon interposers is provided in units and wafers. The report also examines trends in memory packaging, including the future for top memory packages in the package-on-package (PoP) configuration and DRAM stacks with TSVs. Flash memory trends such as the joint Micron/Intel non-volatile memory architecture (3D XPoint™) and Toshiba’s Flash memory stack with TSVs are described. New developments in FO-WLP panel processing are discussed, including activities at Nepes, Powertech Technologies, Samsung Electro-Mechanics, and Unimicron. OSAT financial trends are also analyzed.

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TechSearch International Analysis Predicts Growth for Fan-in and FO-WLP

January 18, 2017

TechSearch International predicts strong market growth for fan-in wafer level packages (WLPs) and fan-out WLP (FO-WLP). Driven by demand for thin, low-profile packages in smartphones, tablets, and wearable devices such as smart watches, fitness bands, and virtual reality headsets, fan-in WLPs are projected to have a >10% growth rate from 2015 to 2020. Starting from shipments of a few hundred million packages in 2015, FO-WLP shows a staggering growth rate of 82% over the five-year period. The use of FO-WLP for RF, audio CODEC, and power management ICs, coupled with Apple’s adoption of TSMC’s InFO FO-WLP as the bottom package-on-package (PoP) in Apple’s iPhone 7, is driving unit volume shipments. Automotive radar, connectivity modules, and other applications promise continued growth for FO-WLPs. Cost-reduction pressures are driving the development of alternatives to reconstituted wafer FO-WLP in the form of large area panel processing and flip chip on coreless or thin core substrates. Chip package interaction (CPI) is analyzed for WLPs and flip chip.

TechSearch International’s new study, Flip Chip and WLP: Market Forecasts and Technology Analysis, provides detailed analysis of the drivers for fan-in WLP, FO-WLP, and flip chip. The detailed analysis is based on the company’s 29-year history of studying markets and critical technology and infrastructure issues.

Driven by small size devices such as filters, low noise amplifiers, power amplifiers, and switches found in smartphones, flip chip growth shows >13% CAGR in unit volume from 2015 to 2020. Documentation of the continued transition to Cu pillar is provided. Flip chip applications, bump types, and pitch trends are based on extensive interviews and research. Flip chip assembly options are discussed. Growth in gold bumping for LCD driver ICs is included. A critical analysis of planned capacity and utilization is provided for each geographic region, showing projections for strong growth in China.

The 115-page report with full references provides forecasts for the flip chip wafer bumping market by application, device type, number of wafers, and die shipments. Merchant and captive capacity is included. Forecasts for fan-in and FO-WLP demand are projected in number of die and wafer shipments. Bumping, wafer level packaging, substrate suppliers, assembly equipment, underfill material, and contract assembly service providers are listed. A set of 78 PowerPoint slides accompanies the report.

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TechSearch International Analysis Shows CSP Growth Remains Strong

October 26, 2016

Despite a slowing growth rate for smartphones, the industry is experiencing strong growth for CSP packages such as QFNs and stacked die CSPs. TechSearch International’s latest CSP market forecast shows an 8% CAGR from 2015 to 2020. One of the categories with the strongest growth is the quad flat no-lead (QFN) package with a CAGR of 8.6%. QFNs are a low-cost, low-profile package found in a wide range of products from automotive and industrial applications to mobile phones and wearable electronics. Power devices continue to drive growth for copper clip versions of the QFN. An analysis of the OSAT market in China provides insight into expansion plans and market share. New advanced packages such as JCAP’s FO-WLP are highlighted.

The analysis is provided in the latest Advanced Packaging Update, a 45-page report with full references and an accompanying set of 36 PowerPoint slides. The report also examines trends in stacked die CSPs, laminate-substrate CSPs, and package-on-package (PoP) with a market forecast for each. PoP trends are analyzed, including the use of TSMC’s FO-WLP for Apple’s A10 application processor. A five-year market forecast for BGAs is also provided.

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Growth in Wearable Electronics Enabled by Advances in Assembly and Packaging

July 27, 2016

Strong market growth is predicted for wearable electronics fueled by new generations of wearables providing greater functionality in the same or smaller form factor, for the same or lower cost. While improvements in IC technologies and software continue to make wearables smarter, advancements in assembly and packaging allow OEMs to meet small form factor, low-power consumption, and low-cost requirements.

One common theme emerging from TechSearch Interntaional’s interviews is that, for a wearable to succeed in the marketplace, it must simplify tasks for its user, not complicate them. That requires greater intelligence from both hardware and software. The high degree of functionality in today’s wearables has been made possible by advanced assembly and packaging technologies, use of wafer-level packages (WLPs) in particular.

Health, sports, and fitness monitoring are driving the wearables market. Basic requirements for activity trackers and smartwatches are: user friendly, comfortable, secure; always on and monitoring; ubiquitous connectivity; durability; and low cost for consumers. The trend in fitness bands and smartwatches is a growing number and variety of sensors.

Many different IC and package types are found in wearable electronics. A typical product contains a microcontroller, a power management device, memory, and a connectivity device (i.e., Wi-Fi or Bluetooth). Wearables also contain MEMS sensors such as accelerometers, gyroscopes, pressure sensors, and compasses, and sometimes sensors for monitoring pulse and blood oxygen saturation, ambient light, and temperature. Packages found in these products include FBGAs, FLGAs, QFNs, stacked die CSPs, WLPs, and system-in-package (SiP). Expanding use of fan-out WLP (FO-WLP) is likely to support form factor, high I/O density, and performance requirements.

TechSearch International’s new 34-page Advanced Packaging Update report with full references provides an updated forecast for FO-WLP in packages and reconstituted wafers, based on new plans for package adoption. Suppliers with panel R&D plans are discussed. The report also contains an analysis of trends in wearable electronics and package adoption as well as new battery technology developments. A set of 28 PowerPoint slides accompanies the report.

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Fan-out WLP Panel Processing: Economic and Technical Challenges

July 18, 2016

Fan-out wafer level packaging (FO-WLP) continues to show growth momentum with multiple parts found in Samsung’s Galaxy phones and many packages expected in Apple’s next iPhone. Under constant pressure to lower cost, a number of companies are researching large area panel processing. TechSearch has released new analysis that examines the economic and technical challenges with the panel approach. Challenges include:

— Managing warpage over a large area as feature size shrinks with materials that interact, especially with different process temperatures

— Die placement throughput over a large area

— Dielectric dispense methods optimized for panels

— Singulation and solder ball attach with large formats

Consortia including Fraunhofer IZM in Berlin, IME in Singapore, and ASMPT in Hong Kong have announced cooperative efforts to help address these challenges. Economic considerations are based on package size and include calculations for the number of panels required monthly with multiple suppliers. TechSearch International’s analysis indicates that larger body sizes potentially have greater economic justification than part sizes of less than 5 mm x 5 mm.

There is no consensus on panel size and many equipment makers are reluctant to develop equipment solely for FO-WLP panel production. Typically, OSATs move equipment from one operation to another based on product demand, but with dedicated panel equipment, re-purposing of equipment is not possible. Investing in a panel process is a risky business for many OSATs that need to see a return on investment (ROI) in an era of increasing price pressures and potentially lower revenues. For many substrate manufacturers, there is no choice but to come up with a product to generate revenue where substrate sales have declined as a result of the switch to FO-WLP. FO-WLP is disruptive technology since thin-film metallization is used to replace the substrate to provide a thinner, lower profile package with high-density interconnect.

TechSearch International’s new 34-page Advanced Packaging Update report with full references provides an updated forecast for FO-WLP in packages and reconstituted wafers, based on new plans for package adoption. Suppliers with panel R&D plans are discussed. The report also contains an analysis of trends in wearable electronics and package adoption as well as new battery technology developments. A set of 28 PowerPoint slides accompanies the report.

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Miniaturization Trends Drive Growth in SiP Market

March 7, 2016

With the proliferation of mobile electronic products and the ongoing push for greater functionality in a smaller area, miniaturization has become a key word for system-in-package (SiP). SiP provides increased functionality in a subsystem that can be more cost-effectively assembled into a system. Miniaturization and other technology trends driving SiP market growth are covered in TechSearch International’s new study, SiP for Mobile and Wearable Applications: Market Forecasts and the Changing Business Model. The thorough analysis is based on the company’s 28-year history of studying markets and critical technology and infrastructure issues.

In many cases SiP provides lower cost and quicker time to market than a system-on-chip (SoC) approach. In today’s world of mobile product introductions that must ramp in four to five months and may only have a lifetime of a year, SiP is essential to the success of new products in this space.

SiPs are found in many products including smartphones, tablets, wearable electronics (including medical products), and other consumer products. High-performance gaming systems, computers, and network systems also use SiP, as do automotive electronics. Future applications may include IoT-related areas such as smart homes, energy products, and industrial automation.

SiP is defined as two or more dissimilar die, typically combined with other components such as passives, filters, MEMS, sensors, and antennas, assembled into a standard footprint package to create a functional system or subsystem. Characteristics of SiPs vary widely and the major attributes can differ depending on the application. In the wireless market, integration, form factor, cost, and shielding are the top interests. For wearable electronics, the drivers are low power, cost, miniaturization, and high yield assembly. In some cases, very highly integrated solutions are needed. Drivers for these include low cost, greater performance, low power, and easy design-in where there is a low entry barrier, with short time-to-market being a critical factor. Automotive SiP features include high power capability, reliability, testability, and form factor. For power modules, the drivers are power efficiency, miniaturization, and EMI shielding.

The 76-page report with full references provides forecasts for the SiP market in units by application and package type. Key requirements for SiP are examined and the roles of design, EMI shielding, and known good die are discussed. The capabilities of OSATs and EMS players are covered. Companies providing SiP assembly services are listed. A set of 49 PowerPoint slides accompanies the report.

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Disruptive Impact of Fan-out WLP Growth Coming for Electronics Industry

November 12, 2015

Fan-out wafer level packaging (FO-WLP) is a disruptive technology that will have a significant impact on the electronics industry in the coming years. WLP has seen strong growth, especially in the mobile devices, because it provides a low-profile package that meets the requirements of many smartphone makers. Billions of WLPs are shipped each year and FO-WLP adoption will drive the number even higher. In its new report, TechSearch International projects an 87% CAGR for FO-WLPs in unit volumes over the next 5 years.

As companies move to the next semiconductor technology node, smaller die are possible, allowing a greater number of die per wafer. At the same time the number of I/Os is increasing, and to route them a conventional WLP would require small diameter solder balls with fine pitch. Qualcomm has published information on the reliability challenges of going to ≤0.35mm pitch with a conventional fan-in WLP.

FO-WLP is an attractive solution that allows companies to continue taking advantage of the powerful economics of die shrink, while also meeting the small form factor, low-profile package requirements of mobile devices. FO-WLP is disruptive technology because there is no substrate and thin-film metallization is used for interconnect instead of bumps or wires. In the case of a face-up process, the die has a thick Cu post, but not a Cu pillar with a solder cap. The use of redistribution layers patterned with semiconductor technology makes it possible to achieve much finer feature sizes ≤5µm lines and spaces, than conventional organic substrate technologies.

With the use of FO-WLP for the logic bottom package in a package-on-package (PoP) configuration, the ultra thin target of <0.8mm PoP can be met. The only lower-profile PoP with memory and logic is a 3D IC memory and logic stack using through silicon vias (TSVs). Such an approach is costly, however and there are no thermal solutions for this stack in mobile applications.

TechSearch International’s new 42-page Advanced Packaging Update report with full references provides forecasts for all types of FO-WLP, including a separate analysis for high-density fan out, in number of parts and reconstituted wafers. Supplier offerings are listed and broken out by face-up and face-down configuration. The report also contains a new market forecast for silicon interposers and a section on automotive safety features and packaging trends, including FO-WLP. A set of 36 PowerPoint slides accompanies the report.

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TechSearch International Analyzes CSP Market Growth: QFNs Remain “Work Horse” of the Industry

August 19, 2015

Driven by use in mobile products such as smartphones, CSPs continue to show growth. TechSearch International’s latest CSP market forecast shows an 11% CAGR from 2014 to 2019. One of the categories with the strongest growth is the quad flat no-lead (QFN) package. QFNs remain the “work horse” of the industry with growth driven by conversion from other leaded packages as well as adoption in new applications. QFNs are found in a wide range of products from automotive and industrial applications to wearable electronics. Increased use of QFNs for power devices continues to drive growth. New versions of the package are being introduced with routable QFNs gaining in popularity as a higher density solution that can support multiple die.

The analysis is provided in the latest Advanced Packaging Update, a 63-page report with full references and an accompanying set of 50 PowerPoint slides. The report also examines trends in stacked die CSPs and package-on-package (PoP) with a market forecast for each. A five-year market forecast for BGAs is provided. Drivers for each application space provide a clear picture of demand for each package type. A special section features thin wafer singulation, including the latest developments in plasma dicing.

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TechSearch International Makes Sense of Package Alphabet Soup

June 3, 2015

With new packages continuously being introduced, TechSearch International’s latest Advanced Packaging Update focuses on making some sense out of the alphabet soup of package options for split die. Application targets range from high-performance solutions for devices such as FPGAs to application processors found in mobile devices. SLIM, SWIFT, EMIB, NTI, and SLIT are high-density substrates without through silicon vias (TSVs). Fan-out wafer level packages (FO-WLPs) also provide an option for a split die package. Roadmaps from FO-WLP suppliers show the transition to finer features.

Package options for power devices are also discussed, including a special section on automotive packages. A detailed analysis focuses on the trends in Cu clip packages for MOSFETs. A double-digit growth rate is projected for this increasingly popular package. Also included is an update on the market for embedded component packages with a new market forecast split into actives and passives.

The detailed analysis is based on the company’s 27-year history of studying markets and critical technology and infrastructure issues in advanced packaging. The 37-page report with full references provides analysis on these important developments. A set of 30 PowerPoint slides accompanies the report.

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TechSearch International Analyzes Flip Chip and Wafer Level Package Growth

March 17, 2015

Shipments of flip chip and wafer level packages (WLPs) continue to increase. TechSearch International’s new study, 2015 Flip Chip and WLP: Emerging Trends and Market Forecasts, provides unparalleled analysis of what’s behind the numbers for the growth of flip chip and wafer level packages (WLPs). Highlighted are the trends in Cu pillar adoption and an explanation for its 29% CAGR. Emerging trends such as the adoption of fan-out WLPs (FO-WLPs) and the trend toward panel level packaging are analyzed in-depth. The detailed analysis is based on the company’s 27-year history of studying markets and critical technology and infrastructure issues.

Flip chip has migrated from mainly high-performance devices found in supercomputers, servers, network systems, and PCs to the explosive growth in filters and RF devices found in today’s smartphones. In units, the compound annual growth rate (CAGR) from 2014 to 2019 is approximately 15%, while in number of wafers the CAGR is only 11% because much of the growth is for small size die. The industry is experiencing a transition from solder bump to Cu pillar, just as it moved from an evaporated bump to a plated process. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice. Details of flip chip applications, bump types, and pitch trends are based on extensive interviews and research. Flip chip assembly choices such as mass reflow and thermocompression bond are discussed and underfill options are provided. Growth in gold bumping for LCD driver ICs is included. A critical analysis of planned capacity and utilization is provided for each geographic region.

Increased demand for thinner, lighter-weight portable products continues to drive WLP growth. These packages offer a small footprint and a low-profile solution that enables ultrathin consumer products such as smartphones, tablets, and wearable electronics. A detailed analysis of WLP shipments by device type, ball count, ball pitch, and thickness is provided. The CAGR for fan-in WLPs in units from 2014 to 2019 is almost 9% for the five-year period, while the CAGR in wafers is 10%. A number of companies plan to adopt FO-WLPs and projected demand and available capacity are highlighted.

The 135-page report with full references provides forecasts for the flip chip wafer bumping market by application, device type, FCIP/FCOB split, number of wafers, and number of die. Merchant and captive capacity is included and projections by bump type and wafer size are provided. Forecasts for WLP demand in number of die, wafers and device type are provided. Bumping, wafer level packaging, substrate suppliers and contract assembly service providers are highlighted with contacts provided. A set of 56 PowerPoint slides accompanies the report.

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TechSearch International Study Details Market Growth for 3D ICs and 2.5D Interposers

September 10, 2014

Major DRAM makers Micron, SK Hynix, and Samsung have announced versions of stacked memory with through silicon vias (TSVs) for high-performance applications. Some CMOS image sensors are also in production with die stacking and TSVs. The remaining question is what is holding back the expansion of 3D IC in other applications? TechSearch International’s 3D IC Gap Analysis: Remaining Issues, Solutions, Market Status provides insight into the remaining technical gaps and business issues holding back the expansion of 3D ICs. Potential solutions from various research organizations and companies are highlighted.

While great progress has been made in via formation and filling, process steps such as debonding during wafer thinning remain problematic. Improvements in process yield that lower cost are necessary if the technology is to expand into new applications. Progress has been made in design tools and methodology, but additional work is required. Low-power design of 3D IC stacks remains in the early stages. Cost-effective thermal solutions are still required for memory/logic and logic/logic stacks. Progress in the testing area has been reported, but work is still needed. Clarity on the issue of responsibility for the assembly and logistics requires resolution. Cost/performance targets must be met, relative to available alternatives. This report examines challenges in adopting the technology today and a timeframe for high-volume manufacturing with details of each application and its requirements.

The 135-page report with full references provides realistic market forecasts. The market forecast for 3D IC is presented in wafers and units. New developments, applications, and a market forecast for (2.5D) interposers are provided in number of wafers and units. The status of interposer suppliers, the role of OSATs, and the potential for laminate and glass interposers are discussed. Alternatives to 3D IC and interposers with TSVs are presented. A set of more than 120 PowerPoint slides accompanies the report.

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TechSearch International Study Details Renewed Interest in Embedded Components

January 15, 2014

Almost every application space in the electronics industry has evolved around a single goal—increase functionality while improving cost/performance. Many strategies and technologies have been introduced, including embedding components inside a printed circuit board or IC package. What's driving today’s renewed interest for embedded active and passive functions?

TechSearch International’s new study, Embedded Components: Why Now? — Markets, Applications, and Technologies, provides unparalleled analysis of the underlying developments and trends in the industry based on the company’s 26-year history of studying the market and critical infrastructure issues.

PCBs and IC packages with embedded passives have been in the market for many years. Dai Nippon Printing started shipping PCBs with embedded passive devices in 2006 and cumulative shipments total hundreds of millions of parts. A smartphone board contains more than 230 passive devices in the main board. Some modules also contain active devices. Casio shipped a power management module with an embedded WLP in its wristwatch in 2006, making it the first wearable electronics application with an embedded component. TI's MicroSiP™ is in volume production with its stand-alone power supply platform (DC-DC voltage converter) for portable applications. Infineon is shipping its DrBlade™ low-voltage DC-DC voltage regulator for computing, telecommunication, servers (Blade and Rack), PCs, and gaming machines.

Formed resistors have been widely employed in the defense and aerospace industry. New applications in the consumer space, telecom, computing, and industrial areas are expanding the market. Planar capacitance has been utilized in the high-performance computing and communication segments for many years. With the higher capacitance levels now available, the market is expanding into IC packages and modules.

This report analyzes the expanding wide range of markets providing insight into the drivers, applications, and future growth. Fan-out wafer level packages are included in the analysis. A discussion of the challenges posed by embedded solutions and the potential impact of the technology on the supply chain is included.

The 134-page report with full references provides an in-depth analysis of the activities of various companies explaining current and future products with specific examples of the use of embedded components. Forecasts are provided for the placed embedded active and passive components, as well as the markets for embedded formed resistors and capacitors. A set of PowerPoint slides accompanies the report.

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SavanSys Solutions and TechSearch International Announce Release of 2.5D and 3D Packaging Cost Model

May 31, 2013

After successful collaboration on cost models for Flip Chip, Wire Bond, Wafer Level Packaging, and other technologies, SavanSys Solutions and TechSearch International announce the release of a new cost trade-off model for 2.5D and 3D packaging technologies. While there are still technical barriers to high volume adoption of 2.5D and 3D packaging solutions, cost remains a primary obstacle. The question is not whether 2.5D and 3D stacks can be built, but rather which applications are appropriate for these technologies based on cost/performance.

The 2.5D & 3D Packaging Cost Trade-off Model covers the total cost and yield from fabrication of the wafer to complete assembly, for both 2.5D and 3D applications. The user is able to edit a variety of parameters, including TSV and interposer characteristics, supplier specific inputs, and die preparation details. For parameters not known or specified, the model will estimate it based on other user entries and the latest industry knowledge. A detailed cost break down of the total process cost is generated for each analysis, allowing the user to pinpoint the exact steps in the process flow that contribute to cost. In addition, detailed manipulation of the process flow is available, allowing the user to disable or enter specific values for process steps.

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TechSearch International Partners with IEEE Women in Engineering Committee (WIE) to Establish IEEE Frances B. Hugle Engineering Scholarship

November 26, 2012

TechSearch International, Inc. announces that in celebration of its 25th anniversary the company partnered with IEEE Women in Engineering Committee (WIE) to establish a scholarship for women going into the field of engineering.

The scholarship, named the IEEE Frances B. Hugle Engineering Scholarship, honors the memory of the distinguished engineer for whom the fund is named. Frances Hugle graduated from the University of Chicago in 1946 with degrees in chemistry, physics, and philosophy and received her M.Sc. degree from the University of Cincinnati. She co-founded Hugle Industries, Siliconix, Stewart Warner Microcircuits, Inc. and Opto-Electronics Devices, Inc. In each of these companies she served as a director of R&D and as chief engineer. She held 16 known patents in the field of electronics and was one of the pioneers in the invention of tape automated bonding (TAB).

To encourage young women to follow in Hugle’s footsteps, IEEE WIE will select one scholar annually to receive a $2,500 scholarship, beginning as early as 2013. The scholarship will be presented to one female in her third year of undergraduate study in an engineering curriculum at an accredited university or college in the United States. Student membership in the IEEE is required.

TechSearch International, Inc. and its founder, E. Jan Vardaman, seeded the Scholarship with a $5,000 donation this year. The objective is to raise $100,000 during the next few years. We hope that others will join us in supporting young women entering the field of engineering by making a donation.

The IEEE Foundation, a tax-exempt 501(c)(3) organization in the United States, is accepting and managing the donations. Donations can be made:
     1. Online at www.ieee.org/donate by selecting the Frances B. Hugle Memorial Fund
     2. By check payable to the IEEE Foundation – Frances B. Hugle Memorial Fund and mailed to IEEE
Foundation, 445 Hoes Lane, Piscataway, NJ, 08854, USA.

To learn more about the IEEE Foundation, visit ieeefoundation.org, call the IEEE Development Office at +1 732-562-3915 or email donate@ieee.org. For more information on IEEE WIE, visit www.ieee.org/women.

The IEEE Foundation provides philanthropic services in support of the IEEE core purpose to foster technological innovation and excellence for the benefit of humanity. To fulfill its role, the IEEE Foundation relies on donations to award grants to charitable organizations with new and innovative projects. It also administers more than 130 donor designated funds that support a variety of educational, humanitarian, historical preservation, and peer recognition programs of IEEE. The IEEE Frances B. Hugle Memorial Fund is administered by the IEEE Foundation, a 501(c)(3) non-profit corporation established in 1973 in the State of New York exclusively to support the scientific and educational purposes of IEEE. Visit www.ieeefoundation.org.

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