Substrate capacity remains tight for both flip chip ball grid array (FC-BGA) substrates and laminate-based chip scale packages (CSPs). Substrate suppliers are adding capacity to meet the demand for FC-BGA substrates for server, graphics processor, and networking applications, but demand continues to outstrip supply. Regardless of the package type—whether silicon interposer, embedded bridge, FO-on-substrate, or Redistribution Layer (RDL) interposer—a laminate substrate is used to form the package. TechSearch International quantifies the gap between manufacturing demand and capacity. The report explores options including yield improvement and substitutes under consideration to solve the crisis. RDL interposers and suppliers are discussed. Panel fan-out options and new players are described.
The new Advanced Packaging Update provides an update on the 5G rollout and the differences between the mmWave and sub-6 GHz smartphones with a look inside Apple’s iPhone 12 Pro. The report also discusses semiconductor shortages, OSAT financials, and the growth of electric vehicles.
The latest APU is a 52-page report with full references and an accompanying set of 50 PowerPoint slides.
The market for heterogeneous integration is projected to grow 10% in number of packages from 2020 to 2025, reaching almost 54 billion packages. Smartphones, wearables, and consumer packages account for the largest number. RF front-end modules including the latest 5G mmWave modules and wireless connectivity modules for Wi-Fi, Bluetooth, and other networks account for nearly half of all heterogeneous integration devices counted in this report. High-performance computing, 5G telecommunications infrastructure, networking, stacked memory, automotive, and medical applications also contribute to the growth in heterogeneous integration packages.
The market for packages using chiplets is expected to show a CAGR of 104% from 2020 to 2025. A chiplet is a functional circuit block and includes reusable IP blocks. It is a physically realized and tested IP with a standard or proprietary communication interface between IP blocks. A chiplet functions with other chiplets, so the design must be co-optimized and the silicon cannot be designed in isolation. An increasing number of companies are turning to chiplets to achieve the economic advantages lost with expensive monolithic scaling, ushering in a new era of smart packaging. The adoption of chiplets represents an inflection point in IC design for CPUs and GPUs; similar to the transition from perimeter pad design to area array with the adoption of flip chip interconnect. It is also possible to have higher core counts and therefore higher performance than with a monolithic design. There is a potential for improved power distribution. Binning the chiplets provides an opportunity to optimize performance even further. Chiplets have been adopted for server processors and AI accelerators, desktop and laptop processors, networking, and adoption in mobile applications such as smartphones and tablets is anticipated. Chiplets can be configured side-by-side or as a 3D stack. The 3D stack may use microbumps, but the direct Cu-to-Cu bonding method provides some of the greatest density and electrical advantages.
Quantifying the Impact of Heterogeneous Integration: Chiplets and SiP is a 130-page report with full references and an accompanying set of 122 PowerPoint slides.
The market for high bandwidth memory (HBM) is projected to grow 49% in wafers, including DRAM and logic layers, from 2020 to 2024. Growth is driven by increased adoption in high-performance computing such as AI, networking, graphics, and future server processors. Solutions to package HBM plus logic include silicon interposers (the most mature), fan-out on substrate using a redistribution layer (RDL), and many bridge solutions. The report examines the increasing number of bridge solutions for RDL structures, silicon interposers, and laminate substrates such as Intel’s embedded Multi-Die Bridge (EMIB) and IBM’s Direct Bonded Heterogeneous Integration (DBHI) silicon-bridge solution.
HBM uses TSVs and µbumps to achieve a 3D format, but the report also examines other 3D stacking methods including the use of hybrid bonding for DRAMs and SRAMs. New offerings from Samsung and TSMC are discussed.
The new Advanced Packaging Update also examines thermal challenges in mobile, high-performance applications such as memory and logic, and photonics. Thermal interface material developments are presented.
TechSearch International’s financial analysis of the OSAT market examines the performance for the first half of 2020 with projected growth for the year. A split of the revenue from assembly vs. test is provided. Also discussed are trends in modularization of smartphones with some of the latest “made in Japan” examples.
The latest APU is a 56-page report with full references and an accompanying set of 57 PowerPoint slides.
The fan-out wafer level package (FO-WLP) market is projected to grow 15.5% in units from 2020 to 2024. Growth is driven by use in mobile devices such as smartphones and smartwatches, automotive radar, and increasing adoption in high-performance computing. Wafer shipments are driven by adoption in AI accelerators, GPU/CPU, and networking applications with increasingly large areas. Foundry and OSAT players are introducing new versions. Alternatives are discussed, including silicon interposers, embedded bridge, and RDL interposers.
The new Advanced Packaging Update examines developments in integrated passives and the growing demand for high-performance substrates. A special section on integrated photonics is included, answering the question of “why now?” TechSearch International, Inc. details a number of factors that have come together to drive the adoption of integrated photonics, explaining that it is not a volume play, but rather a strategic move to support the sales of hardware and services.
TechSearch International’s new financial analysis of the OSAT market shows the importance of investments in advanced packaging.
The latest APU is a 70-page report with full references and an accompanying set of 62 PowerPoint slides.
Despite the economic downturn caused by the fight against the Covid-19 virus, there are some potential growth areas this year. Growth in advanced packaging continues for datacenter servers, AI accelerators, and 5G infrastructure. The shelter-in-place requirements have driven out-of-season demand for game consoles, commercial and educational laptops and tablets, and monitors. The pandemic is driving increased production of ventilators and wider adoption of telemedicine. Trends in the adoption of industrial IoT continue.
TechSearch International’s new report examines the type of packages that will benefit from this growth and provides a forecast for BGA and CSPs. In 2019, TechSearch International reports that approximately 140 billion units shipped (not including wafer level packages). Despite the impact of lower smartphone unit volumes in 2020 some specialty packages show growth. The report examines drivers for QFN packages with a special focus on Cu clip, as well as molded interconnect substrates (MIS). Examples of the type of CSPs used in a variety of products based on teardowns are provided. New developments in high-performance packages are discussed, including silicon interposers, embedded bridge, and fan-out on substrate.
A financial analysis of the OSAT market show the importance of investments in advanced packaging, especially SiP.
The latest APU is a 70-page report with full references and an accompanying set of 70 PowerPoint slides.
Continued monolithic integration is expensive and can suffer from the defect density yield loss associated with large die. As a result, an increasing number of companies are turning to new architectures using chiplets to achieve the economic advantages lost with expensive monolithic scaling. TechSearch International’s new Advanced Packaging Update (APU) details many advantages of chiplets and provides examples in production today as well as a preview of future end products. The report also provides an update on embedded bridge developments and a forecast for high bandwidth memory (HBM).
TechSearch International’s new report peeks inside Apple’s latest iPhone with a count of the wafer level packages (WLPs) and finds a surprising amount of underfill. Quarterly and annual OSAT financial trends are examined.
The latest APU is a 45-page report with full references and an accompanying set of 52 PowerPoint slides.
Many smartphone manufacturers are offering 5G handsets in a bid to increase mobile phone sales. Several 5G-compatible smartphones are in mass production and more are scheduled for release this year. Smartphones sales have stagnated so OEMs and carriers are pushing 5G development and deployment with the hopes that customers will be enticed to upgrade their phones.
These early 5G phones are primarily designed to enhance 4G LTE by adding sub-6GHz frequency spectrum. Support for the millimeter-wave (mmWave) version of 5G, which many consider to be the “true” 5G, is limited as rollout of the technology is still in its infancy.
By examining the design and construction of several 5G smartphones, TechSearch International has spotted important trends for the packaging industry, including more chips and packages in 5G handsets than 4G phones. For example, the Samsung Galaxy S10 5G has almost 2x more packages than the S10/S10+ for the RF front-end and baseband functions, and that is just to support sub-6GHz 5G connectivity. Additional RFFE packages are required for mmWave 5G.
TechSearch International’s latest Advanced Packaging Update provides details about RFFE designs and packages, transceiver and modem comparisons, and additional antenna and PMIC requirements for 5G handsets.
The latest Advanced Packaging Update also discusses packages found in basic feature phones. The report is 83 pages in length with full references and an accompanying set of 41 PowerPoint slides.
Driven by advanced packaging substrate needs, the industry has reached an inflection point in IC substrate manufacturing. Increasing I/O counts are driving substrate layer counts to more than 20. Larger die sizes and multiple die mounted on the substrate are driving the need for larger body sizes, up to 100 mm x 100 mm. Some companies use a silicon interposer with multiple redistribution layers (RDLs) to provide the connection between logic and high bandwidth memory (HBM). Others use fan-out on substrate with RDLs. A number of companies are considering new RDL on organic solutions with 2µm line width and spaces and Intel is exploring an expanded role for its Embedded Multi-die Interconnect Bridge (EMIB). Several companies are making investments in fab-like processing equipment for the next generation IC packaging substrates. These developments are described and a forecast for high-density substrates is provided in TechSearch International’s newest Advanced Packaging Update.
TechSearch International’s annual survey on substrate design rules is highlighted, with special coverage of suppliers of laminate flip chip BGA and CSP substrates worldwide. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish.
The latest Advanced Packaging Update is an 83-page report with full references and an accompanying set of 41 PowerPoint slides.
TechSearch International predicts strong market growth for fan-in wafer level packages (WLPs) and fan-out WLPs (FO-WLPs). Despite lower growth for smartphones, growth continues as the number of WLPs per handset increase. WLPs are increasingly adopted in tablets, and wearable devices such as smart watches, fitness bands, and virtual reality headsets. Fan-in WLPs are projected to grow at an 8.5% CAGR from 2018 to 2022. FO-WLP's adoption continues in products ranging from smartphones to automotive and the package shows a growth rate of almost 37% over the four-year period. Cost-reduction pressures are driving the development of alternatives to reconstituted wafer FO-WLP in the form of large area panel processing and the first product can be seen in the new Samsung smart watch. An analysis of the market growth in units, wafers, and panels is provided for fan-in and fan-out. The market is divided into standard-density, high-density, and panel.
TechSearch International’s new study, 2019 Flip Chip and WLP: Trends and Market Projections, provides detailed analysis of the drivers for fan-in WLP, FO-WLP, and flip chip. The detailed analysis is based on the company's 31-year history of studying markets and critical technology and infrastructure issues.
Demand for flip chip in applications ranging from large die for AI accelerators to small die for amplifiers and filters is provided. Cu pillar is increasingly used for many devices. Demand continues for both 300mm and 200mm bumping. Market projections in units and wafers are provided. Flip chip growth shows an 8.3% CAGR in unit volume from 2018 to 2022. Growth in gold bumping is also included. A critical analysis of planned capacity and utilization is provided for each geographic region, showing projections for strong growth in China.
The 124-page report with full references provides forecasts for the flip chip wafer bumping market by application, device type, number of wafers, and die shipments. Merchant and captive capacity is included. Forecasts for fan-in and FO-WLP demand are projected in number of die and wafer shipments. A set of 90 PowerPoint slides accompanies the report.
The high cost of moving to the next semiconductor technology node is changing the role of packaging and assembly in the electronics industry. Heterogeneous integration has become the solution to achieve the economic advantages that were previously met with silicon scaling. TechSearch International’s new report describes these packaging options, including silicon interposers, fan-out on substrate, and organic solutions such as Intel’s EMIB. Homogeneous packaging solutions such as AMD’s multichip package are also discussed. The report explains the reason for adoption in each application and provides market projections. A roadmap of future 3D packaging trends is presented and new concepts such as Intel’s Foveros are discussed.
Changes in RF package adoption are examined. Antenna-in-Package solutions for 5G are introduced and a market forecast is provided. A special section examines trends in 3D printing, highlighting printed antennas.
The latest Advanced Packaging Update is a 41-page report with full references and an accompanying set of 48 PowerPoint slides.