Volume 2-0721

July 2021
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This second volume of the Advanced Packaging Update presents new developments in integrated photonics. An updated analysis of the substrate capacity shortage is presented with a focus on build-up substrates for flip chip packages. New substrate developments, including high-density RDL interposers are highlighted. TechSearch International’s annual survey on substrate design rules is presented with special coverage of suppliers of laminate flip chip BGA and CSP substrates worldwide. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish
  • Contents…
    • 1 Industry and Economic Trends
      • 1.1 Economic Trends
        • 1.1.1 U.S. Macroeconomic Trends
      • 1.2 Shortages
        • 1.2.1 Semiconductor Demand and Shortages
        • 1.2.2 Passives
      • 1.3 TSMC's Outlook
    • ​2 OSAT Financials
      • 2.1 Market Overview
      • 2.2 OSAT Market Performance
      • 2.3 Outlook
    • ​3 Substrate Capacity Issues
      • 3.1 FC-BGA Substrates
        • 3.1.1 Drivers for Substrate Demand
        • 3.1.2 Capacity Expansion
    • 4 New Substrate Developments
      • 4.1 Ceramic
      • 4.2 Glass Substrates
        • 4.2.1 AGC
        • ​4.2.2 Corning
        • 4.2.3 DaiNippon Printing
        • 4.2.4 LPKF
        • 4.2.5 Samtec
        • 4.2.6 SCHOTT
        • 4.2.7 Mosaic Microsystems
      • 4.3 Redistribution Layers
        • 4.3.1 Samsung
        • 4.3.2 TSMC
          • 4.3.2.1 SoIS
          • 4.3.2.2 InFO_oS
          • 4.3.2.3 CoWoS®-R
        • 4.3.3 Unimicron
        • 4.3.4 OSATs
          • 4.3.4.1 Amkor
          • 4.3.4.2 ASE
          • 4.3.4.3 SPIL
    • ​​5 Trends in Co-Packaged Photonics
      • 5.1 Datacenter Requirements and Roadmaps
        • 5.1.1 Facebook
        • 5.1.2 Microsoft
        • 5.1.3 Intel
        • 5.1.4 Broadcom
        • 5.1.5 Cisco Systems
        • 5.1.6 Nvidia
      • 5.2 Manufacturing Embedded Photonics
        • 5.2.1 GlobalFoundries
        • 5.2.2 Cadence Design Systems
        • 5.2.3 TSMC
        • 5.2.4 IME
        • 5.2.5 IBM
    • ​6 Substrate Design Rules
      • 6.1 Today's Laminate Feature Size
      • 6.2 Company Design Rules
        • 6.2.1 ACCESS Semiconductor
        • 6.2.2 ASE Materials
        • 6.2.3 AT&S
        • 6.2.4 Daeduck
        • 6.2.5 Daisho Denshi
        • 6.2.6 Fujitsu Interconnect Technologies
        • 6.2.7 Haesung DS
        • 6.2.8 Ibiden
        • 6.2.9 Kinsus Interconnect Technology
        • 6.2.10 Korea Circuit Company
        • 6.2.11 Kyocera International
        • 6.2.12 LG Innotek
        • 6.2.13 Nan Ya PCB
        • 6.2.14 Samsung Electro-Mechanics
        • 6.2.15 Shennan Circuits
        • 6.2.16 Shinko Electric Industries
        • 6.2.17 Simmtech
        • 6.2.18 Toppan Printing
        • 6.2.19 TTM Technologies
        • 6.2.20 Unimicron Technology
    • ​Appendix: Substrate Suppliers
    • References
  • Figures…
    • 1.1 Monthly U.S. housing starts.
    • 4.1 CBHC substrate structure.
    • 4.2 Cu bridge process sequence for glass interposer.
    • 4.3 PLP interposer process flow.
    • 4.4 SoIS structure.
    • 4.5 Organic interposer vs. silicon interposer.
    • 5.1 Silicon photonic evolution from FPP to on-board and co-packaged.
    • 5.2 GF's hybrid laser integration on a monolithic SiPh platform.
    • 5.3 Photonic engine.
    • 5.4 FO-WLP integration for EIC-PIC.
    • 5.5 Through-Silicon Interposer integration for EIC-PIC.
    • 5.6 Co-packaged photonic module.
    • 5.7 Load cases for bending fibers.
    • 5.8 Bending fiber parameters.
  • Tables…
    • 2.1 Revenue Growth for Top 20 OSATs
    • 2.2 Revenue Change YoY for Top 20 OSATs
    • 3.1 Selected Substrate Makers' Gross Margin
    • 3.2 FC-BGA Substrate Supply and Demand
    • 5.1 Metrics for Co-Packaged Optics
    • 5.2 Benefits of CPO
    • 5.3 Light Source Options for Photonics
    • 5.4 GlobalFoundries' Silicon Photonics Test Capability
    • 5.5 Understanding the Packaging Requirement
    • 6.1 Selected Build-up FC-PBGA Substrate Suppliers
    • 6.2 Selected Build-up FC-CSP Substrate Suppliers
    • 6.3 Design Rules for ACCESS Coreless Substrates
    • 6.4 Design Rules for ACCESS FC-CSP Substrates
    • 6.5 Design Rules for ACCESS Wire Bond CSP Substrates
    • 6.6 Design Rules for ASE PBGA/CSP Substrates
    • 6.7 Design Rules for AT&S FC-PBGA Substrates
    • 6.8 Design Rules for Daeduck FC-CSP Substrates
    • 6.9 Design Rules for Daeduck Thin Build-up WB Substrates
    • 6.10 Design Rules for Daeduck FC-PBGA Substrates
    • 6.11 Design Rules for Daisho Denshi PBGA/CSP Substrates
    • 6.12 Design Rules for FICT FC-PBGA Substrates
    • 6.13 Design Rules for Ibiden FC-PBGA Substrates
    • 6.14 Design Rules for Ibiden Coreless Substrates
    • 6.15 Design Rules for Kinsus FC-PBGA Substrates
    • 6.16 Design Rules for Kinsus FC-CSP Substrates
    • 6.17 Design Rules for Kinsus PBGA/CSP Substrates
    • 6.18 Design Rules for Kinsus Coreless Substrates
    • 6.19 Design Rules for KCC FC-CSP Substrates
    • 6.20 Design Rules for KCC UT-CSP Substrates
    • 6.21 Design Rules for Kyocera FC-PBGA Substrates
    • 6.22 Design Rules for Kyocera FC-CSP Substrates
    • 6.23 Design Rules for Kyocera Coreless Substrates
    • 6.24 Design Rules for LG Innotek CSP Substrates
    • 6.25 Design Rules for LG Innotek FC-CSP Substrates
    • 6.26 Design Rules for Nan Ya PCB FC-PBGA Substrates
    • 6.27 Design Rules for Nan Ya PCB PBGA/CSP Substrates
    • 6.28 Design Rules for Nan Ya FC-CSP Substrates
    • 6.29 Design Rules for Nan Ya PCB FC-PBGA Coreless Substrates
    • 6.30 Design Rules for SEMCO FC-PBGA Substrates
    • 6.31 Design Rules for SEMCO PBGA/CSP Substrates
    • 6.32 Design Rules for SEMCO FC-CSP Substrates
    • 6.33 Design Rules for SCC PBGA/CSP Substrates
    • 6.34 Design Rules for Shinko Electric FC-PBGA Substrates
    • 6.35 Design Rules for Shinko Electric FC-CSP Substrates
    • 6.36 Design Rules for Shinko Electric Coreless Substrates
    • 6.37 Design Rules for Simmtech PBGA/CSP Substrates
    • 6.38 Design Rules for Simmtech Coreless Substrates
    • 6.39 Design Rules for Toppan FC-PBGA Substrates
    • 6.40 Design Rules for Toppan Coreless Substrates
    • 6.41 Design Rules for CoreEZ® Substrates
    • 6.42 Design Rules for HyperBGA® Substrates
    • 6.43 Design Rules for PBGA Substrates
    • 6.44 Design Rules for MicroFlex (Polyimide)
    • 6.45 Design Rules for Unimicron FC-PBGA Substrates
    • 6.46 Design Rules for Unimicron FC-CSP Substrates
    • 6.47 Design Rules for Unimicron PBGA/CSP Substrates

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