With the move to each new silicon node, Moore’s law (observation) has fulfilled the economic and technological promises of density, speed, power, and cost scaling. Our current silicon designs will not be able to achieve these same economic advantages. As the industry moves to the next silicon nodes, on-package integration is needed to achieve the economic advantages that were previously met with silicon scaling. The industry is experiencing diminishing returns to monolithic silicon scaling. Moving forward, the industry will need to:
- Design some components in the most advanced semiconductor nodes
- Use this chip(s) in combination with others in a package that provides the desired function in a more cost effective manner
- Combine into a single package the die functions that can be fabricated in older nodes at lower cost
- Reuse IP to reduce cost
As a result, new packaging solutions are being developed with many different formats that very often include heterogeneous integration (HI). HI includes solutions in which some die functions are fabricated on bleeding edge nodes, combined with other die fabricated on less expensive older nodes and linked together in the package. It is driven by the need to add diverse functionality (often realized on different IP on silicon nodes from multiple different suppliers), improved silicon yield resiliency, and the continued need for integration. HI includes system-in-package (SiP) and chipsets.
This report describes the drivers for growth in each segment and package types for different applications. Market projections for chiplets and SiP are provided. An analysis of the impact of the use of chiplets instead on monolithic die integration is provided. Critical material needs for packaging and assembly are identified and the roles for OSAT and foundry are discussed. Investment requirements and the supply chain for chiplets are highlighted.
A set of PowerPoint slides is included with the detailed analysis.