Quantifying the Impact of Heterogeneous Integration: Chiplets and SiP

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With the move to each new silicon node, Moore’s law (observation) has fulfilled the economic and technological promises of density, speed, power, and cost scaling. Our current silicon designs will not be able to achieve these same economic advantages. As the industry moves to the next silicon nodes, on-package integration is needed to achieve the economic advantages that were previously met with silicon scaling. The industry is experiencing diminishing returns to monolithic silicon scaling. Moving forward, the industry will need to:

  • Design some components in the most advanced semiconductor nodes
  • Use this chip(s) in combination with others in a package that provides the desired function in a more cost effective manner
  • Combine into a single package the die functions that can be fabricated in older nodes at lower cost
  • Reuse IP to reduce cost
As a result, new packaging solutions are being developed with many different formats that very often include heterogeneous integration (HI). HI includes solutions in which some die functions are fabricated on bleeding edge nodes, combined with other die fabricated on less expensive older nodes and linked together in the package. It is driven by the need to add diverse functionality (often realized on different IP on silicon nodes from multiple different suppliers), improved silicon yield resiliency, and the continued need for integration. HI includes system-in-package (SiP) and chipsets.

This report describes the drivers for growth in each segment and package types for different applications. Market projections for chiplets and SiP are provided. An analysis of the impact of the use of chiplets instead on monolithic die integration is provided. Critical material needs for packaging and assembly are identified and the roles for OSAT and foundry are discussed. Investment requirements and the supply chain for chiplets are highlighted.

A set of PowerPoint slides is included with the detailed analysis.
  • Contents...
    • Executive Summary
      • Heterogeneous Applications
      • Chiplets
      • Key Requirements for Heterogeneous Integration
      • HI Market Projections
    • 1 Introduction
      • 1.1 What is Heterogeneous Integration?
      • 1.2 What is System-in-Package?
      • 1.3 What is a Chiplet?
    • 2 Heterogeneous Integration
      • 2.1 AI Accelerators
        • 2.1.1 Alibaba
        • 2.1.2 Baidu
        • 2.1.3 Intel
        • 2.1.4 Google
        • 2.1.5 NVIDIA
        • 2.1.6 Xilinx
      • 2.2 Network Switches
      • 2.3 Integrated Photonics
      • 2.4 GPUs and CPUs
      • 2.5 Drivers for Package Selection
      • 2.6 Silicon Interposers
        • 2.6.1 Samsung
        • 2.6.2 TSMC
      • 2.7 Embedded Bridge and FO Solutions
        • 2.7.1 Amkor
        • 2.7.2 ASE
        • 2.7.3 IBM Research and AI Hardware
        • 2.7.4 Intel
        • 2.7.5 SPIL
        • 2.7.6 TSMC
        • 2.7.7 Tongfu Microelectronics
      • 2.8 RDL Interposers
        • 2.8.1 Samsung
        • 2.8.2 TSMC
      • 2.9 Laminate Substrate SiPs
        • 2.9.1 IBM Assembly and Test Services
        • 2.9.2 JCET
        • 2.9.3 Intel
      • 2.10 3D Heterogeneous Integration
        • 2.10.1 High Bandwidth Memory
        • 2.10.2 GLOBALFOUNDRIES
        • 2.10.3 Samsung
        • 2.10.4 TSMC
    • 3 Chiplet Drivers and Applications
      • 3.1 Package Configurations
        • 3.1.1 2D
        • 3.1.2 3D
      • 3.2 Mobile: Smartphones, Tablets, Laptops
        • 3.2.1 Intel's Foveros
      • 3.3 High Performance Computing: Server, AI, and Networking
        • 3.3.1 AMD
        • 3.3.2 Ayar Labs, Cisco, and Photonics
        • 3.3.3 Intel
        • 3.3.4 Mediatek
        • 3.3.5 Samsung
        • 3.3.6 TSMC
      • 3.4 Military and Aerospace
        • 3.4.1 DARPA
        • 3.4.2 SHIP
      • 3.5 Research Organizations
        • 3.5.1 CEA Leti
        • 3.5.2 IME
        • 3.5.3 Fraunhofer IZM
        • 3.5.4 IMEC
        • 3.5.5 L3 MATRIX
        • 3.5.6 UCLA
    • 4 SiP Drivers and Applications
      • 4.1 RF Front-End and Connectivity Modules
        • 4.1.1 Mobile RF FEMs
        • 4.1.2 IoT Wireless Modules
      • 4.2 MEMS-Based Sensor Modules
        • 4.2.1 E-Compass Sensor Modules
        • 4.2.2 Motion Sensor Modules
        • 4.2.3 Pressure Sensor Modules
        • 4.2.4 MEMS Microphones
        • 4.2.5 Proximity and Ranging Sensor Modules
      • 4.3 Power Modules
        • 4.3.1 Analog Devices
        • 4.3.2 STMicroelectronics
        • 4.3.3 Texas Instruments
        • 4.3.4 Apple and USI Partnership
        • 4.3.5 Shift from Silicon to WBG Transistors
        • 4.3.6 Copper Clip
        • 4.3.7 Embedded Die Packages
        • 4.3.8 IPM Devices
      • 4.4 BGA SSDs
      • 4.5 Automotive Heterogeneous Integration
        • 4.5.1 Microcontroller/Processor SiP
        • 4.5.2 Airbag Sensors
        • 4.5.3 Tire Monitoring Sensors
        • 4.5.4 V2X Communications Module Examples
        • 4.5.5 ISELED Smart Lighting Modules
      • 4.6 Medical Electronics
        • 4.6.1 Pacemakers and Defibrillators
        • 4.6.2 Neurostimulation
        • 4.6.3 Imaging
        • 4.6.4 Hearing Devices
        • 4.6.5 Fitness Bands
        • 4.6.6 Stretchable and Printable Medical Electronics
    • 5 Design
      • 5.1 Chiplet Design
        • 5.1.1 Chiplet Interfaces
      • 5.2 Chiplet Thermal Analysis
      • 5.3 3D Design Challenges
    • 6 Assembly and Materials
      • 6.1 Singulation
      • 6.2 Die Handling
      • 6.3 Hybrid Direct Bonding
        • 6.3.1 CEA Leti
        • 6.3.2 Fraunhofer Institute
        • 6.3.3 IMEC
        • 6.3.4 Xperi Corporation
        • 6.3.5 Equipment Suppliers
      • 6.4 Thermal Materials
      • 6.5 Substrates
        • 6.5.1 Capacity Shortages
        • 6.5.2 Substrate Materials
    • 7 Test and Inspection
      • 7.1 Test
        • 7.1.1 HBM
        • 7.1.2 Probing Chiplets
        • 7.1.3 Reliability Assessments
    • 8 Infrastructure Investment
      • 8.1 Chiplet Assembly Infrastructure
    • 9 Market Forecasts
  • Figures…
    • 2.1 Intel co-packaged optics Ethernet switch
    • 2.2 Samsung’s I-Cube™
    • 2.3 CoWoS for heterogeneous integration
    • 2.4 Samsung’s R-Cube™
    • 2.5 Samsung’s H-Cube™
    • 2.6 SiP for 5G base station
    • 2.7 SoIC for low temperature memory + SOC
    • 3.1Intel’sFoveros
    • 3.2 AMD chiplets design for processor
    • 3.3 Intel GPU with chiplets
    • 3.4 Chiplet package advantages
    • 3.5 F2F vs. F2B vs. side-by-side
    • 3.6 Immersion-in-Memory-Computing
    • 3.7 Fine pitch bumping for chiplet integration
    • 4.1 Block diagram for Nordic’s nRF9160 SiP for cellular IoT
    • 4.2 ON’s RSL10 Bluetooth LE SiP with built-in antenna
    • 4.3 Structure of proposed “hybrid” package for IMUs
    • 4.4 Cross-section of ST’s LPS33HW water-resistant sensor
    • 4.5 Schematic drawing of Infineon’s DPS368 package
    • 4.6 Vesper’s piezoelectric MEMS microphone sensing element
    • 4.7 LTM4620 dual DC/DC 􏰁Module® regulator
    • 4.8 STGAP1AS galvanically isolated gate driver SiP
    • 4.9 TI molded power module form factors
    • 4.10 Automotive infotainment SiP
    • 6.1 IMEC hybrid bonding concept
    • 6.2 Collective D2W process flow
    • 7.1 Determine probe pad locations for SoIC
  • Tables…
    • 1 Chiplet Package Market Forecast
    • 2 Heterogeneous Integration Market
    • 2.1 High-Performance Heterogeneous Integration Examples
    • 2.2 IBM's Embedded Bridge
    • 2.3 5G Infrastructure Examples
    • 2.4 BW Density and Power: HBM vs. LT-SoIC (8-high)
    • 3.1 InFO-R versus InFO-L
    • 3.2 SoIC Compared to 2.5D and Conventional 3D
    • 3.3 SoIC Bonding vs. Nominal 3DIC with Solder Microbump Stacking
    • 3.4 Comparison of Lite-IO and Prior Works
    • 3.5 Advanced Microelectronics Assembly Specifications
    • 3.6 RF Centric Specifications
    • 4.1 Examples of RF Front-End Modules for Mobile
    • 4.2 Components in Avago AFEM-8200 Compared to AFEM-8100
    • 4.3 Components in Qorvo QM78092 Compared to QM78062
    • 4.4 Area Required for RFFE Modules on iPhone Main Boards
    • 4.5 Components in USI Wi-Fi/Bluetooth Modules
    • 4.6 Examples of Wireless Connectivity Modules
    • 4.7 Examples of Multi-Die Electronic Compass Sensors
    • 4.8 Suppliers of Multi-Die E-Compass Chips
    • 4.9 Types of MEMS Motion Sensors
    • 4.10 Examples of Recent MEMS Motion Sensors
    • 4.11 Suppliers of Board-Mount MEMS Motion Sensors
    • 4.12 Examples of Pressure Sensors
    • 4.13 Suppliers of Pressure Sensors for Mobile and Wearables
    • 4.14 Suppliers for MEMS Microphones for Mobile, Wearables, and IoT
    • 4.15 Examples of MEMS Microphones
    • 4.16 Examples of Optical Proximity Sensors
    • 4.17 Examples of ToF Sensors for Ranging
    • 4.18 Suppliers of Optical Proximity and ToF Ranging Sensors
    • 4.19 Examples of Power Modules
    • 4.20 Comparison of SESUB and a-EASI Technologies
    • 4.21 Suppliers of BGA SSDs
    • 4.22 Kioxia BG4 BGA SSD Specifications Compared to BG3
    • 4.23 LiDAR Detector Roadmap
    • 4.24 Examples of Automotive-Related SiPs
    • 4.25 Renesas R-Car Cockpit SiPs
    • 4.26 ISELED Alliance Members
    • 6.1 Die to Die vs. Wafer to Wafer
    • 8.1 Heterogeneous Integration Assembly Service Providers
    • 9.1 Chiplet Package Market Forecast
    • 9.2 Heterogeneous Integration
    • 9.3 SiP Descriptions (Mobile, Wearable, Consumer)
    • 9.4 Heterogeneous Integration Descriptions (Computing, Communications, Automotive)
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brochure
  • Published February 2021
  • 131 pages
  • 27 figures / 44 tables
  • 122 PowerPoint slides
  • $8,750 corporate license
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