Volume 2-0726

July 2026
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This second volume of the Advanced Packaging Update includes an analysis of OSAT financials. Data center growth, energy and water use, and shortages of components, assembly, and materials are described. A discussion of orbital data centers is provided. Developments in hybrid bonding are discussed along with drivers and projections for application adoption timing. Remaining challenges are discussed. A special section is devoted to challenges in high-performance computing including large substrates; developments in glass core substrates and remaining challenges; and alternatives including ceramic core and silicon. TechSearch International’s annual survey on substrate design rules is presented, with special coverage of suppliers of laminate flip chip BGA and CSP substrates worldwide. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish.
  • Contents…
    • 1 Industry and Economic Trends
      • 1.1 Economic Outlook
        • 1.1.1 China's Economy
        • 1.1.2 U.S. Macroeconomic Trends
      • 1.2 Semiconductor Industry Trends
    • 2 OSAT Financial Analysis
      • 2.1 Market Overview
      • 2.2 OSAT Market Performance
      • 2.3 Company Highlights
        • 2.3.1 ASE Technology Holdings
        • 2.3.2 Amkor Technology
        • 2.3.3 JCET
        • 2.3.4 Tongfu Microelectronics
        • 2.3.5 Powertech Technology
        • 2.3.6 Tianshui Huatian Technology
        • 2.3.7 UTAC
        • 2.3.8 KYEC
        • 2.3.9 Hana Micron
        • 2.3.10 ChipMOS
      • 2.4 Outlook
    • 3 Data Center Growth Challenges
      • 3.1 Power and Water Concerns and Solutions
      • 3.2 Potential Solutions
      • 3.3 Orbiting Data Centers
        • 3.3.1 Shortages
          • 3.3.1.1 Memory
          • 3.3.1.2 Build-up Substrates
          • 3.3.1.3 Substrate Core Materials
          • 3.3.1.4 Assembly Capacity
    • 4 Hybrid Bonding Developments
      • 4.1 Hybrid Bonding Providers
      • 4.2 Hybrid Bonding Applications
        • 4.2.1 Computing
          • 4.2.1.1 AMD
          • 4.2.1.2 Apple
          • 4.2.1.3 Broadcom
          • 4.2.1.4 Intel
        • 4.2.2 Co-packaged Optics
        • 4.2.3 High Bandwidth Memory
        • 4.2.4 Future Applications
      • 4.3 Challenges and Solutions
      • 4.4 Hybrid Bonding Equipment
    • 5 HPC Packaging Challenges
      • 5.1 Large Body Substrate Challenges
      • 5.2 Glass Core Substrates
        • 5.2.1 Company Activities
          • 5.2.1.1 Absolics
          • 5.2.1.2 AKM Meadville
          • 5.2.1.3 BOE
          • 5.2.1.4 Dai Nippon Printing
          • 5.2.1.5 FICT
          • 5.2.1.6 Fraunhofer IZM
          • 5.2.1.7 Intel
          • 5.2.1.8 LG Innotek
          • 5.2.1.9 Qorvo
          • 5.2.1.10 Samsung Electro-Mechanics
          • 5.2.1.11 Shinko Electric
          • 5.2.1.12 Simmtech
          • 5.2.1.13 Sony
          • 5.2.1.14 3D Glass Solutions
          • 5.2.1.15 Toppan
          • 5.2.1.16 Unimicron
        • 5.2.2 Glass Core TGV R&D Progress
      • 5.3 Alternative Core Materials
        • 5.3.1 ACCM
        • 5.3.2 Applied Materials
        • 5.3.3 Daeduck
        • 5.3.4 Kinsus
        • 5.3.5 Kyocera
        • 5.3.6 Niterra
        • 5.3.7 RDL Interposer Alternative
    • 6 Substrate Design Rules
      • 6.1 Substrate Trends
      • 6.2 Company Design Rules
        • 6.2.1 ACCESS Semiconductor
        • 6.2.2 ASE Materials
        • 6.2.3 AT&S
        • 6.2.4 BRAI Technology
        • 6.2.5 Daeduck
        • 6.2.6 Daisho Denshi
        • 6.2.7 FICT
        • 6.2.8 GS Swiss PCB
        • 6.2.9 Haesung DS
        • 6.2.10 Ibiden
        • 6.2.11 Kinsus Interconnect Technology
        • 6.2.12 Korea Circuit Company
        • 6.2.13 Kyocera International
        • 6.2.14 LG Innotek
        • 6.2.15 Meiko
        • 6.2.16 Nan Ya PCB
        • 6.2.17 R&D Altanova
        • 6.2.18 Samsung Electro-Mechanics
        • 6.2.19 Shennan Circuits
        • 6.2.20 Shenzhen Fastprint Circuit Tech
        • 6.2.21 Shinko Electric Industries
        • 6.2.22 Simmtech
        • 6.2.23 Toppan
        • 6.2.24 TTM Technologies
        • 6.2.25 Unimicron
    • Appendix: Substrate Suppliers
    • References
  • Figures…
    • 4.1 D2W pressure-less bonding steps.
  • Tables…
    • 2.1 Quarterly Revenue of Top 20 Publicly Traded OSATs (millions)
    • 3.1 Build-up Substrate Supply and Demand
    • 3.2 T-Glass Capacity and Demand
    • 4.1 Hybrid Bonders
    • 5.1 Glass Core Substrate Demonstrations
    • 5.2 Glass with TGVs and RDL
    • 6.1 Selected Build-up Substrate Suppliers
    • 6.2 Selected Build-up FC-CSP Substrate Suppliers
    • 6.3 Design Rules for ACCESS FC-BGA Substrates
    • 6.4 Design Rules for ACCESS Via-post Coreless Substrates
    • 6.5 Design Rules for ACCESS FC-CSP/SiP Substrates
    • 6.6 Design Rules for ASE PBGA/CSP Substrates
    • 6.7 Design Rules for AT&S FC-PBGA Substrates
    • 6.8 Design Rules for BRAI FC-PBGA Substrates
    • 6.9 Design Rules for Daeduck FC-CSP/SiP Substrates
    • 6.10 Design Rules for Daeduck Thin WB Substrates
    • 6.11 Design Rules for Daeduck FC-PBGA Substrates
    • 6.12 Design Rules for Daisho Denshi PBGA/CSP Substrates
    • 6.13 Design Rules for Daisho Denshi FC-BGA Substrates
    • 6.14 Design Rules for FICT FC-PBGA Substrates
    • 6.15 Design Rules for Ibiden FC-PBGA Substrates
    • 6.16 Design Rules for Kinsus FC-PBGA Substrates
    • 6.17 Design Rules for Kinsus FC-CSP Substrates
    • 6.18 Design Rules for Kinsus PBGA/CSP Substrates
    • 6.19 Design Rules for Kinsus Coreless Substrates
    • 6.20 Design Rules for KCC FC-CSP Substrates
    • 6.21 Design Rules for KCC UT-CSP Substrates
    • 6.22 Design Rules for Kyocera FC-PBGA Substrates
    • 6.23 Design Rules for Kyocera FC-CSP Substrates
    • 6.24 Design Rules for LG Innotek CSP Substrates
    • 6.25 Design Rules for LG Innotek FC-CSP Substrates
    • 6.26 Design Rules for LGIT FC-PBGA Substrates
    • 6.27 Design Rules for Meiko FC-PBGA Substrates
    • 6.28 Design Rules for Meiko PCB PBGA Substrates
    • 6.29 Design Rules for Nan Ya PCB FC-PBGA Substrates
    • 6.30 Design Rules for Nan Ya PCB PBGA/CSP Substrates
    • 6.31 Design Rules for Nan Ya FC-CSP Substrates
    • 6.32 Design Rules for Nan Ya PCB FC-PBGA Coreless Substrates
    • 6.33 Design Rules for R&D Altanova FC-PBGA Substrates
    • 6.34 Design Rules for SEMCO FC-PBGA Substrates
    • 6.35 Design Rules for SEMCO PBGA/CSP Substrates
    • 6.36 Design Rules for SEMCO FC-CSP Substrates
    • 6.37 Design Rules for SCC PBGA/CSP Substrates
    • 6.38 Design Rules for Fastprint FC-BGA Substrates
    • 6.39 Design Rules for Shinko Electric FC-BGA/LGA Substrates
    • 6.40 Design Rules for Shinko Electric FC-CSP Substrates
    • 6.41 Design Rules for Shinko Electric Coreless Substrates
    • 6.42 Design Rules for Simmtech PBGA/CSP Substrates
    • 6.43 Design Rules for Simmtech Coreless Substrates
    • 6.44 Design Rules for Toppan FC-PBGA Substrates
    • 6.45 Design Rules for CoreEZ® Substrates
    • 6.46 Design Rules for HyperBGA® Substrate
    • 6.47 Design Rules for TTM FC-PBGA Substrates
    • 6.48 Design Rules for Unimicron FC-PBGA Substrates
    • 6.49 Design Rules for Unimicron FC-CSP Substrates
    • 6.50 Design Rules for Unimicron PBGA/CSP Substrates

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