3D IC Gap Analysis

Remaining Issues, Solutions, Market Status
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Major DRAM makers Micron, SK Hynix, and Samsung have announced versions of stacked memory with through silicon vias (TSVs) for high-performance applications. Some CMOS image sensors are also in production with die stacking and TSVs. The remaining question is what is holding back the expansion of 3D IC in other applications?

While great progress has been made in via formation and filling, process steps such as debonding during wafer thinning remain problematic. Improvements in process yield that lower cost are necessary to expand into new applications. Progress has been made in design tools and methodology, but additional work is required. Cost-effective thermal solutions are still required for memory/logic and logic/logic stacks. Progress in the testing area has been reported, but work is still needed.

This report examines challenges in adopting the technology and a timeframe for high-volume manufacturing with details of each application and its requirements. The report with full references provides market forecasts for 3D ICs in wafers and units. New developments, applications, and a market forecast for (2.5D) interposers are provided in number of wafers and units. The status of interposer suppliers, the role of OSATs, and the potential for laminate and glass interposers are discussed.

A set of PowerPoint slides accompanies the report.
  • Contents…
    • Executive Summary
    • 1 Introduction
    • 2 Status: Progress
      • 2.1 Design
      • 2.2 Via Fabrication Process Improvements
      • 2.3 Test
      • 2.4 Risk Assumption and Future Business Issues
      • 2.5 Cost
      • 2.6 Outlook
    • 3 Design Challenges and EDA Tools
      • 3.1 Pathfinding Tools
      • 3.2 EDA Tools
    • 4 Temporary Bond/Debond​
      • 4.1 DeBond Methods
      • 4.2 Bond/Debond Equipment
      • 4.3 Materials for Wafer Bond/Debond
    • 5 Assembly Challenges​
      • 5.1 Assembly Methods and Developments
        • 5.1.1 Die-to-Die Bonding for 3D ICs​
        • 5.1.2 Wafer-to-Wafer Bonding
        • 5.1.3 2.5D Assembly
      • 5.2 Micro Bump Trends
      • 5.3 Bonding Equipment Developments
      • 5.4 Underfill Materials
      • 5.5 On-Board Stack Assembly
    •  6 Infrastructure and Supply Chain
      • 6.1 Foundries
      • 6.2 OSATs
        • Amkor, ASE, PTI, Shinko Electric, SPIL,
          STATS ChipPAC​
      • 6.3 Silicon Interposers
        • ALLVIA, Dai Nippon Printing, EPWorks, GLOBALFOUNDRIES, IBM, Inotera, IMT, IPDiA, Shinko Electric, Silex, TSMC, Novati, TowerJazz, UMC
      • 6.4 Glass Interposers
      • 6.5 Laminate Interposers
    • 7 Thermal
      • 7.1 Reduced Power Consumption Designs
      • 7.2 Thermally-Aware 3D IC Design Tools
        • 7.2.1 Cielution
        • 7.2.2 Docea Power
        • 7.2.3 North Carolina State University
      • 7.3 Cooling Developments
        • 7.3.1 DARPA’s ICECool
    • ​9 Reliability
      • 9.1 TSV Structures and Impact on Reliability
      • 9.2 Reliability Data on 2.5D Structures
        • 9.2.1 Silicon Interposers
      • 9.3 Reliability Measurement of TSVs
      • 9.4 Electromigration and Thermomigration
    • 10 Standards
      • 10.1 Standards Development Organizations
    • 11 Alternatives to 3D ICs
      • 11.1 High-Performance and Alternative Stacking
      • 11.2 Mobile Devices
    • 12 3D IC Applications and Markets
      • 12.1 Image Sensors
      • 12.2 DRAM
        • 12.2.1 Demonstrations and Products
        • 12.2.2 Applications and Market Size
      • 12.3 Processors and Memory for Mobile Devices
      • 12.4 Flash Memory
      • 12.5 Logic Stacking with TSVs
      • 12.6 Automotive Sensors
      • 12.7 Market Projections​
    • 13 2.5D Interposer Market Forecast
      • 13.1 FPGA Introduction
      • 13.2 Networking Applications
      • 13.3 GPUs
      • 13.4 Servers
      • 13.5 Tablets
      • 13.6 2.5D Interposer Market
    • 14 Research Institute Activities
      • ASET, CEA-LETI, Georgia Tech, GINTI, HDPUG, KAIST, Fraunhofer, IME, IMEC, ITRI, NCAP, RTI, SEMATECH, STARC, Si2
  • Figures and Tables (partial list)…
    • 3D IC adoption timeline
    • Trade-offs in back-side RDL for a logic-on-logic stack
    • Signal and power integrity analysis on a silicon interposer
    • Wafer chipping resulting from too soft adhesive
    • Mechanical debonding
    • Direct Bond Interconnect (DBI®) hybrid bonding
    • Bump pitch trends for TSV wafers
    • Chip on interposer on substrate
    • Thermal issue for 3D IC vs. PoP
    • Validation results of CielSpot-CTM simulation
    • EMIB conceptual drawing
    • Sony’s image sensor with TSV
    • SK Hynix HBM
    • Micron’s packaged die stack
    • Interposer Adoption Timeline and Barriers
    • Shipments of 3D ICs with TSVs (including image sensors)
    • TSV Interposer Market Projections
    • 3D IC Applications: Drivers, Status, and Barriers
    • Commercial EDA Tools
    • Bond/Debond Equipment Offerings
    • Temporary Bonding Material Options
    • High Precision Bonders
    • Foundry Process Offerings
    • OSATs Process Offerings
    • Silicon Interposer Suppliers
    • Coarse Pitch and Fine Pitch Silicon Interposers
    • Advantages and Challenges of Glass Interposers
    • Design Rule Targets for 2.5D Glass Interposers
    • Advantages and Challenges of Organic Interposers
    • Selected Organic Interposer Suppliers and Technology
    • Selected Thermally-Aware Design Solutions for 3D-TSV
    • Probe Card Examples
    • MCM, Interposer, and 3D IC Options
    • TSV DRAM Memory Solutions
    • 3D IC with TSV 300mm Wafer Shipments
    • Selected Applications for Silicon Interposers
    • Interposer Adoption Timeline and Barriers
Stacks Image 26243
brochure
  • Published September 2014
  • 135 pages
  • 17 figures / 31 tables
  • 120 PowerPoint slides
  • $4,995 single user
    $8,000 corporate license
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