Volume 1-0518

May 2018
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This issue of the Advanced Packaging Update features special coverage of outsourced semiconductor assembly and test (OSAT) financials. A detailed financial analysis of the industry is presented. A discussion of fan-out wafer level package (FO-WLP) trends, including TSMC’s latest portfolio and an update on large-area panel activities are provided. The growing applications for 3D sensing are discussed along with details on VCSEL technology. Developments in integrated photonics packaging trends are discussed.
  • Contents…
    • 1 Industry and Economic Trends
      • 1.1 Economic Trends
      • 1.2 Semiconductor Sector
    • ​2 OSAT Financial Analysis
      • 2.1 Assembly and Test Revenue
        • 2.1.1 Outlook for Revenue Growth
          • 2.1.1.1 Mobile Communication and 5G Rollout
          • 2.1.1.2 Growth in China
          • 2.1.1.3 Memory Trends
          • 2.1.1.4 2018 Expansion Examples
      • ​2.2 OSAT CAPEX
    • 3 FO-WLP Developments
      • 3.1 TSMC's Portfolio Expands
        • 3.1.1 5G Mobile Platform
        • 3.1.2 High-Performance Computing
      • 3.2 Large Area Processing Panels
      • 3.3 ASE and Deca Technologies
      • 3.4 Nepes
      • 3.5 Powertech Technology
      • 3.6 Samsung Electro-Mechanics
      • 3.7 Unimicron
    • 4 3D Sensing Modules
      • 4.1 VCSEL
    • 5 Integrated Photonics Packaging
      • 5.1 Drivers for Integrated Photonics
      • 5.2 Technology Options
        • 5.2.1 InP
        • 5.2.2 Silicon
        • 5.2.3 Polymer Materials
        • 5.2.4 Glass
      • 5.3 Silicon Photonics Process
      • 5.4 Integrated Photonics Packaging
        • 5.4.1 Packaging Challenges
        • 5.4.2 Standards and Design Challenges
      • 5.5 Consortia
        • 5.5.1 AIM Photonics
        • 5.5.2 IMEC
        • 5.5.3 IRT Nanoelec
        • 5.5.4 PETRA
        • 5.5.5 PIXAPP Photonic Packaging Pilot Line
      • 5.6 Company Activities
        • 5.6.1 Amkor Technology
        • 5.6.2 AOI Core
        • 5.6.3 ASE
        • 5.6.4 Cisco
        • 5.6.5 ColorChip
        • 5.6.6 Fabrinet
        • 5.6.7 Finisar
        • 5.6.8 Fujitsu
        • 5.6.9 GLOBALFOUNDRIES
        • 5.6.10 Hewlett Packard Enterprise Labs
        • 5.6.11 Huawei
        • 5.6.12 IBM
        • 5.6.13 Infinera
        • 5.6.14 Integra Technologies and Juniper
        • 5.6.15 Intel
        • 5.6.16 Lightwave Logic
        • 5.6.17 Luxtera
        • 5.6.18 Mellanox Technologies
        • 5.6.19 POET Technologies
        • 5.6.20 Rockley Photonics
        • 5.6.21 TSMC
        • 5.6.22 EDA Tool Makers
    • References
  • Figures…
    • 1.1 Monthly U.S. housing starts.
    • 3.1 Hybrid FC-CSP versus MUST.
    • 3.2 Fingerprint sensor in panel FO-WLP.
    • 4.1 Modules of the Face ID system in iPhone X.
    • 4.2 Cross-section of TriLumina's VCSEL array structure.
    • 5.1 Waveguide propagation loss as a function of wafer process.
    • 5.2 QSFP module and cut-away showing module board.
    • 5.3 Bandwidths at various interfaces of a package on a PCB.
    • 5.4 IMEC's optical module on a silicon photonics interposer.
    • 5.5 Dragonfly™ mid-board optical module.
    • 5.6 Silicon photonics package evolution at PETRA.
    • 5.7 Prototype sub-system with PETRA's optical I/O cores.
    • 5.8 Silicon photonics transceiver chip and I/O core cross-sections.
    • 5.9 Side and top view of 8° oblique cone-shaped optical pin array.
    • 5.10 Optical I/O core receiver with electrical and optical I/O.
    • 5.11 Hybrid optical/electrical package substrate with polymer waveguides.
    • 5.12 PIC integrated with bridge assembly.
    • 5.13 Edge coupling optical fiber interconnects.
    • 5.14 Grating coupling optical fiber interconnects.
    • 5.15 100Gbps silicon photonics chipset in QSFP module.
    • 5.16 Chip-on-chip and Chip on-wafer.
    • 5.17 200Gbps silicon photonics chipset in embedded module.
    • 5.18 GLOBALFOUNDRIES silicon photonics foundry roadmap.
    • 5.19 Flip chip CMOS/silicon photonics interposer.
    • 5.20 IBM parallelized fiber array assembly.
    • 5.21 IBM compliant polymer interface.
    • 5.22 Self-aligned photonic flip chip assembly.
    • 5.23 Silicon photonics compared to an InP PIC.
    • 5.24 Infinera's ICE5 optical engine with two InP PIC modules.
    • 5.25 Infinera's ICE6 optical engine with co-packaged DSP and PIC.
    • 5.26 Intel's hybrid silicon laser.
    • 5.27 Lightwave Logic's photonics product roadmap.
    • 5.28 Luxtera transceiver manufacturing and test flow.
    • 5.29 Light source assembly including laser diode, ball lens, and
      Faraday rotator.
    • 5.30 Luxtera's concept for ASIC/transceiver integration.
  • Tables…
    • 1.1 Top 20 OSAT Revenues
    • 2.2 OSAT CAPEX Trends
    • 3.1 Apple's A10, A11, and Potential Future Processors
    • 3.2 Hybrid FC-CSP versus MUST
    • 3.3 RF Transceiver in FC-CSP versus InFO
    • 3.4 InFO_AiP for 5G RF FEM (mmWave)
    • 3.5 FO-WLP Panel Production Plans
    • 4.1 3D Sensing Supply Chain
    • 5.1 Benchmark of Silicon Photonics Transceiver Engines
    • 5.2 Material Choices for an Optical Platform
    • 5.3 Integrated Photonics with Glass Interposer

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